revision history rev - a datasheet released. may 05 , 1999 rev - b added more detailed dimension information of pcb , full data sheet changed to new format. jan 11 , 2000 ug516w724(8)4hk(s)g 45388 warm springs blvd. fremont, ca. 94539 tel: (510) 668-2088 fax: (510) 661-2788 support@unigen.com re-tek- 332_mt .com .com .com 4 .com u datasheet
45388 warm springs blvd. fremont, ca. 94539 tel: (510) 668-2088 fax: (510) 661-2788 support@unigen.com 1 of 7 re-tek- 332_mt general description features pin assignment pin # signal 1 vss 2 dq0 3 dq1 4 dq2 5 dq3 6 vcc 7 dq4 8 dq5 9 dq6 10 dq7 11 dq8 12 vss 13 dq9 14 dq10 15 dq11 16 dq12 17 dq13 18 vcc 19 dq14 20 dq15 21 dq16 22 dq17 23 vss 24 nc 25 nc 26 vcc 27 we0 28 cas0 29 nc 30 ras0 31 oe0 32 vss 33 a0 34 a2 35 a4 36 a6 37 a8 38 a10 39 a12 40 vcc 41 nc 42 nc pin # signal 43 vss 44 oe2 45 ras2 46 cas4 47 nc 48 we2 49 vcc 50 nc 51 nc 52 dq18 53 dq19 54 vss 55 dq20 56 dq21 57 d q22 58 dq23 59 vcc 60 dq24 61 nc 62 nc 63 nc 64 nc 65 dq25 66 dq26 67 dq27 68 vss 69 dq28 70 dq29 71 dq30 72 dq31 73 vcc 74 dq32 75 dq33 76 dq34 77 dq35 78 vss 79 pd1 80 pd3 81 pd5 82 pd7 83 id0 84 vcc pin # signal 85 vss 86 dq36 87 dq37 88 dq38 89 dq39 90 vcc 91 dq40 92 dq41 93 dq42 94 dq43 95 dq44 96 vss 97 dq45 98 dq46 99 dq47 100 dq48 101 dq49 102 vcc 103 dq50 104 dq51 105 dq52 106 dq53 107 vss 108 nc 109 nc 110 vcc 111 nc 112 cas1 113 nc 114 ras1 115 nc 116 vss 117 a1 118 a3 119 a5 120 a7 121 a9 122 a11 123 nc 124 vcc 125 nc 126 b0 pin # signal 127 vss 128 nc 129 ras3 130 cas5 131 nc 132 pde 133 vcc 134 nc 135 nc 136 dq54 137 dq55 138 vss 139 dq56 140 dq57 141 dq58 142 dq59 143 vcc 144 dq60 145 nc 146 nc 147 nc 148 nc 149 dq61 150 dq62 151 dq63 152 vss 153 dq64 154 dq65 155 dq66 156 dq67 157 vcc 158 dq68 159 dq69 160 dq70 161 dq71 162 vss 163 pd2 164 pd4 165 pd6 166 pd8 167 id1 168 vcc the ug516w724(8)4hk(s)g is a 16,7774,216 bits by 72 edo dram module with ecc . the ug516w724(8)4hk(s)g is assembled using 18 pcs of 16mx4 4k\8k refresh drams in 32-pin soj/tsop package,and 2 pcs abt163244 buffers in 240mil package mounted on a 168-pin buffered printed circuit board. single 3.3 +/- 0.3v power supply extended data out mode cas-before-ras refresh capability ras-only and hidden refresh capability 4096 \ 8192 refresh cycles every 64 \ 128 ms 12/12 \ 13/11 addressing (row / column) lvttl compatible inputs and output buffered input except ras and dq new jedec standard pinout & buffered pdpin pcb:height (1250mil),double sided component absolute maximum ratings 128m bytes (16m x 72) dram 168pin dimm with ecc based on 16 m x 4 pin names function a0, b0, a1 - a11 address input(4k ref) a0, b0, a1 - a12 address input(8k ref) dq0 - dq71 data in/out we0 , we2 read/write enable oe0 , oe2 output enable ras0 ~ ras3 row address strobe cas0, 1,4,5 column address strobe v cc power(+3.3v) v ss ground nc no connection pde presence detect enable pd1 - 8 presence detect id0 , 1 id bit pin names voltage relative to gnd -1.0 to +4.6 v operating temperature 0 to +70 c storage temperature -55 to +150 c short-circuit output current 50ma power dissipation 18.0 w part identification part number ref.cycle UG516W7244HKG soj tsop 4k 4k 8k 8k ug516w7244hsg ug516w7284hkg ug516w7284hsg packages tsop soj ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ug516w724(8)4hk(s)g .com .com .com .com 4 .com u datasheet
functional block diagram vcc vss 0.1 or 0.22uf capacitor under each dram to all drams ras0 we0 oe0 a0 dq0 dq1 dq2 dq3 *a1-a11(a12) dq0 dq1 dq2 dq3 cas0 u0 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 u1 dq0 dq1 dq2 dq3 dq8 dq9 dq10 dq11 u2 dq0 dq1 dq2 dq3 dq12 dq13 dq14 dq15 u3 dq0 dq1 dq2 dq3 dq16 dq17 dq18 dq19 u4 dq0 dq1 dq2 dq3 dq20 dq21 dq22 dq23 u5 dq0 dq1 dq2 dq3 dq24 dq25 dq26 dq27 u6 dq0 dq1 dq2 dq3 dq28 dq29 dq30 dq31 u7 dq0 dq1 dq2 dq3 dq32 dq33 dq34 dq35 u8 ras2 we2 oe2 b0 dq0 dq1 dq2 dq3 *a1-a11(a12) dq36 dq37 dq38 dq39 cas4 u9 dq0 dq1 dq2 dq3 dq40 dq41 dq42 dq43 u10 dq0 dq1 dq2 dq3 dq44 dq45 dq46 dq47 u11 dq0 dq1 dq2 dq3 dq48 dq49 dq50 dq51 u12 dq0 dq1 dq2 dq3 dq52 dq53 dq54 dq55 u13 dq0 dq1 dq2 dq3 dq56 dq57 dq58 dq59 u14 dq0 dq1 dq2 dq3 dq60 dq61 dq62 dq63 u15 dq0 dq1 dq2 dq3 dq64 dq65 dq66 dq67 u16 dq0 dq1 dq2 dq3 dq68 dq69 dq70 dq71 u17 *a12 is used for 8k ref. only. ug516w724(8)4hk(s)g 45388 warm springs blvd. fremont, ca. 94539 tel: (510) 668-2088 fax: (510) 661-2788 support@unigen.com 2 of 7 re-tek- 332_mt .com .com .com .com 4 .com u datasheet
physical dimension 168 pin dimm module units : inches (millimeters) tolerances : + .005(.13) unless otherwise specified _ 5.250 5.014 0.050 0.039 .002 0.01max (0.25 max) r 0.079 (r 2.000) 0.250 (6.350) 1.450 (36.830) 2.150 (54.61) 0.350 0 . 1 0 0 m i n ( 2 . 5 4 0 m i n ) 0 . 7 0 0 ( 1 7 . 7 8 0 ) (1.000 . 050) (1.270 ) 0 . 1 0 0 m i n ( 2 . 5 4 0 m i n ) detail c .118dia .004 (3.000dia .100) (8.890) a b c 0.250 (6.350) .450 (11.430) 4.550 (115.57) 0.157 0.004 (4.000 0.100 ) 0.054 (1.372) (127.350) (133.350) 1 . 2 5 0 ( 3 1 . 7 5 ) 0.118 (3.000) 0.250 (6.350 ) detail a 0.1230 .0050 (3.125 .125) detail b 0.079 .0040 (2.000 .100) 0 . 1 1 8 ( 3 . 0 0 0 ) 0.250 (6.350 ) 0.1230 .0050 (3.125 .125) 0.079 .0040 (2.000 .100) ( back view ) ( front view ) 0.050 0.0039 (1.270 0.190max (4.83max tsop 0.350max (8.89max soj ug516w724(8)4hk(s)g 45388 warm springs blvd. fremont, ca. 94539 tel: (510) 668-2088 fax: (510) 661-2788 support@unigen.com 3 of 7 re-tek- 332_mt .com .com .com .com 4 .com u datasheet
c absolute maximum ratings the following information is based on micron component p/n m t4c16m4h9(g3) only . i cc1 , i cc3 , i cc4 and i cc6 are dependent on output loading and cycle rates. specified values are obtained with the output open. i cc is specified as an average current. in i cc1 and i cc3 , address can be changed maximum once while ras =v il . in i cc4 , address can be changed maximum once within one edo mode cycl e time, t hpc . * note : * permanent device damage may occur if absolute maximum rati ngs are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of th is data sheet. exposure to absolute maximum rating condition s for in tended periods may affect device reliability. item symbol rating unit voltage on any pin relative v ss voltage on v cc supply relative to v ss storage temperature power dissipation short circuit output current v in , v out v cc t stg p d i os -1.0 to +4.6 -1.0 to +4.6 -55 to +150 18 50 v v w ma recommended operating conditions (voltage referenced to v ss , t a = 0 to 70 ) item symbol min typ max unit supply voltage ground input high voltage input low voltage v cc v ss v ih v il 3.0 0 2.0 -0.3 3.3 0 - - 3.6 0 v cc +0.3 0.8 v v v v dc and operating characteristics (recommended operating conditions unless otherwise noted) i cc1 i cc2 i cc3 i cc4 i cc5 i cc6 i( il) i( ol) v oh v ol symbol speed ug516w7284hk(s)g unit min max min max i cc1 -5 -6 - - 2080 1920 - - 2720 2560 ma ma i cc2 all - 16 - 16 ma i cc3 -5 -6 - - 2400 1920 - - 2400 1920 ma ma i cc4 -5 -6 - - 2080 1920 - - 2720 2560 ma ma i cc5 all - 8 - 8 ma i cc6 -5 -6 - - 2560 2400 - - 2560 2400 ma ma i i(l) i o(l) all -36 -5 36 5 -36 -5 36 5 ua ua v oh v ol all 2.4 - - 0.4 2.4 - - 0.4 v v : operating current * ( ras , cas , address cycling @ t rc =min) : standby current ( ras = cas = w =v ih ) : ras only refresh current * ( cas =v ih , ras cycling @ t rc =min) : extended data out mode current * ( ras =v il , cas cycling : t hpc =min) : standby current ( ras = cas = w =v cc -0.2v) : cas -before- ras refresh current * ( ras and cas cycling @ t rc =min) : input leakage current (any input 0 v in v cc +0.3v, all other pins not under test=0 v) : output leakage current(data out is disabled, 0v v out v cc ) : output high voltage level (i oh = -2ma) : output low voltage level (i ol = 2ma) c ug516w7244hk(s)g ug516w724(8)4hk(s)g 45388 warm springs blvd. fremont, ca. 94539 tel: (510) 668-2088 fax: (510) 661-2788 support@unigen.com 4 of 7 re-tek- 332_mt .com .com .com .com 4 .com u datasheet
ac characteristics capacitance (t a = 25 , v cc =3.3v, f = 1mhz) item symbol min max unit input capacitance[a0, b0 , a1 - a12] input capacitance[ we0 , we2 , oe0 , oe2 ] input capacitance[ ras0 - ras3 ] input capacitance[ cas0 ,1, 4, 5 ] input/output capacitance[dq0-dq71] c in1 c in2 c in3 c in4 cdq - - - - - 80 56 35 35 10 pf pf pf pf pf (0 t a 70 , v cc =3.3v 0.3v. see notes 1,2.) test condition : v ih /v il =2.2/0.7v, v oh /v ol =2.0/0.8v, output loading c l =100pf parameter symbol -5 -6 unit note min max min max random read or write cycle time t rc 84 104 ns read-modify-write cycle time t rwc 116 140 ns access time from ras t rac 50 60 ns 3,4,10 access time from cas t cac 13 15 ns 3,4,5,13 access time from column address t aa 25 30 ns 3,10,13 cas to output in low-z t clz 0 0 ns 3,13 transition time(rise and fall) t t 2 50 2 50 ns 2 ras precharge time t rp 30 40 ns ras pulse width t ras 50 10k 60 10k ns ras hold time t rsh 13 15 ns 13 cas hold time t csh 38 45 ns cas pulse width t cas 8 10k 10 10k ns ras to cas delay time t rcd 11 14 ns 4,13 ras to column address delay time t rad 9 12 ns cas to ras precharge time t crp 5 5 ns row address set-up time t asr 0 0 ns 13 row address hold time t rah 9 10 ns column address set-up time t asc 0 0 ns column address hold time t cah 8 10 ns read command set-up time t rcs 0 0 ns read command hold referenced to cas t rch 0 0 ns 8 read command hold referenced to ras t rrh 0 0 ns write command hold time t wch 8 10 ns 7 write command pulse width t wp 5 5 ns write command to ras lead time t rwl 13 15 ns write command to cas lead time t cwl 8 10 ns data set-up time t ds 0 0 ns data hold time t dh 8 10 ns refresh period (8k) t ref 128 64 ms write command set-up time t wcs 0 0 ns 7 cas to w dealy time t cwd 28 35 ns 7 ras to w dealy time t rwd 67 79 ns 7,13 c c + _ 9,13 13 8,13 13 13 10,13 13 ug516w724(8)4hk(s)g 45388 warm springs blvd. fremont, ca. 94539 tel: (510) 668-2088 fax: (510) 661-2788 support@unigen.com 5 of 7 re-tek- 332_mt refresh period (4k) t ref 64 128 9,13 ms .com .com .com .com 4 .com u datasheet
ac characteristics (0 c t a 70 c, v cc =3.3v 0.3v. see notes 1,2.) parameter symbol -5 -6 unit note min max min max column address to w delay time t awd 42 49 ns 7 cas setup time( cas -before- ras refresh) t csr 5 5 ns 13 cas hold time( cas -before- ras refresh) t chr 8 10 ns 13 ras to cas precharge time t rpc 5 5 ns 13 access time from cas precharge t cpa 28 35 ns 3,13 hyper page cycle time t hpc 20 25 ns 12 hyper page read-write cycle time t hprwc 47 56 ns 12 cas precharge time(hyper page cycle) t cp 8 10 ns ras pulse width (hyper page cycle) t rasp 50 125k 60 125k ns w to ras precharge time(c-b-r refresh) t wrp 8 10 ns 13 w to ras hold time(c-b-r refresh) t wrh 8 10 ns 13 oe access time t oea 12 15 ns 13 oe to data delay t oed 15 18 ns 13 output buffer turn off delay time from oe t oez 0 12 0 15 ns 13 oe command hold time t oeh 8 10 ns output data hold time( c -b- r refresh) t doh 10 10 ns 13 w to data delay t wed 20 20 ns 13 oe to cas hold time t och 5 10 ns cas hold time to oe t cho 5 5 ns oe precharge time t oep 5 5 ns w pulse width (hyper page cycle) t wpe 10 10 ns ug516w724(8)4hk(s)g 45388 warm springs blvd. fremont, ca. 94539 tel: (510) 668-2088 fax: (510) 661-2788 support@unigen.com 6 of 7 re-tek- 332_mt .com .com .com .com 4 .com u datasheet
1998. all rights reserved. all product specifications are su bject to change without notice. the materials are provided " as is " without any express or implied warranty of any kind. in no e vent shall unigen be liable for any damages whatsoever arisi ng out of the use or inability to use these materials. c o notes an initial pause of 200us is required after power-up followe d by any 8 ras -only or cas -before- ras refresh cycles before proper device operation is achieved. input voltage levels are v ih /v il . v ih (min) and v il (max) are ref- erence levels for measuring timing of input signals. transi- tion times are measured between v ih (min) and v il (max) and are assumed to be 5ns for all inputs. measured with a load equivalent to 1 ttl loads and 100pf. operation within the t rcd (max) limit insures that t rac (max) can be met. t rcd (max) is specified as a reference point only. if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . assumes tha t rcd 3 t rcd (max). this parameter defines the time at which the output achieves the open circuit condition and is not referenced to v oh or v ol . t wcs , t rwd , t cwd , t awd and t cpwd are not restrictive operat- ing parameter. they are included in the data sheet as electr i- cal characteristics only. if t wcs t wcs (min) the cycle is an early write cycle and the data out pin will remain high impe d- ance for the duration of the cycle. if t rwd t rwd (min), t cwd 3 t cwd (min), t awd 3 t awd (min) and t cpwd 3 t cpwd (min). the cycle is a read-modify-write cycle and the data out will contain data read from the selected cell. if neither of the above sets of conditions is satisfied, the condition of data out(at access time) is indeterminate. either t rch or t rrh must be satisfied for a read cycle. these parameters are referenced to the cas leading edge in early write cycles. operation within the t rad (max) limit insures that t rac (max) can be met. t rad (max) is specified as reference point only. if t rad is greater than the specified t rad (max) limit, then access time is controlled by t aa . if ras goes high before cas high going, the open circuit condition of the output is achieved by cas high going. if cas goes high before ras high going , the open circuit condition of the output is achieved by ras going. t asc 3 6ns. the timing skew from the dram to the dimm resulted from the addition of buffers. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 12. 13. 11. ug516w724(8)4hk(s)g 3 3 45388 warm springs blvd. fremont, ca. 94539 tel: (510) 668-2088 fax: (510) 661-2788 support@unigen.com 7 of 7 re-tek- 332_mt .com .com .com 4 .com u datasheet
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